I think your bed is warping slightly as it heats up, which is normal. Set your bed temp to 105 for half an hour before starting your print and see if it still happens. If you have a V0 or other manually levelled printer, get the bed to 105 before levelling.

What are your bed temps for PLA and ASA? Does it still happen if you preheat the bed? If you rotate the print, does the rough spot follow the rotation?

An alkaline AA may have more capacity, but the LiPo has lower internal resistance and it’s electrolyte is flammable. The worst the alkaline would do it shorted or punctured is get warm and poop out KOH.

$ :|wc -c 0 $ touch /tmp/f; :>>/tmp/f; wc -c /tmp/f 0 /tmp/f

“fill angle” under infill settings.

Yep. I can get ASA down to 12% with an ambient 50%RH using that method.

There are some models out there for wedges with reverse Bowden fittings so you can keep it cracked open all the time.

Try running your dryer with the lid propped open a bit. Most Sunlu dryers don’t have a way to get rid of the humid air pulled out of the filament.

I got one of those ten years ago when they came out. It was a little ugly but it was snappy and could go for a couple of days on a charge. I can’t say the same for any of the WearOS watches I had since then.

V.35 or IEEE-488

Nah, this is Apple. It’s got to be the most expensive: Lemo medical grade.

N connector to SMA, and hardline to USB-C.

But one of those chonky third party ones with the buttons on the sides, and have a FireWire cable coming out of there too for that 2003 feel

Apple historically can’t or won’t bring mixed signal design in-house. It could be related to patents, standards compliance, or the much more complicated silicon design, DV, and test for analog vs digital. It’s not just the modem either. The bulk of Cirrus Logic’s business nowadays is making audio, haptics, and focus servo chips for Apple, and if Apple ever went vertical with those components Cirrus would collapse overnight. Yet Apple has been buying custom audio chips from them for over 30 years, so obviously this isn’t a new trend.

If you ever have the chance to use an old Apple II computer, run a text mode program, wait til the owner is looking in the other direction and turn the power off and back on quickly.

For about a second, before you hear the loud BOOP and the screen clears, you’ll see whatever was on the screen just before you powered it off. But a few characters will be corrupted. Try it again, and wait a half a second longer than before. More characters will be corrupted.

For that brief second you’re looking at the contents of the video RAM, then the ROM (Apple called what we call BIOS now “ROM”) clears the contents and puts up the familiar text banner. The longer the power stays off, the more the contents of those RAM cells decay, and any bit flip will show up as a different character at the corresponding location on the screen.

On a side note, there was an article in the early '80s in Circuit Cellar by Steve Ciarcia showing how you could make a rudimentary digital camera by prying the top off a DRAM chip (some were ceramic with metal lids, or just metal cans) and adding a CCTV camera lens at the right distance. Light can deplete the charge in DRAM cells even faster, and by writing all 1s to the memory, exposing it to light, and reading back the contents, you could get a black and white image of whatever’s shining on the chip.

Modern RAM just needs to be told to refresh. The device itself will go through the refreshing process. But the whole array needs to be refreshed, there’s no LRU scheme to tell what bank or row was last accessed.

Starting with DDR3 it’s not so easy. Density is so high that reading or writing one row affects cells in adjacent rows. Partial target row refresh (PTRR) counters this, where any access of a row is followed by a refresh of adjacent rows. Flaws in this process in early DDR3 controllers was at the heart of rowhammer exploits, where repeated accesses to a memory location could work out what’s stored in physically adjacent memory, even if it’s not privileged. IIRC DDR4 pulled the PTRR process into the RAM’s built in refresh circuitry so it’s transparent to the memory controller.

RAM storage cells are tiny, fast, and don’t degrade over time. Each cell can store an electrical charge that distinguishes a 0 from a 1. However they forget their contents whenever they’re being read or if they’re not topped up occasionally. RAM needs to be refreshed by writing back contents after a cell is read, and making sure that periodically every cell in the chip is read and written back. Without constant power to refresh, RAM forgets its contents.

Flash is similar to RAM because it also stores data as a charge. To make the contents last without power and survive being read, each cell is tied to the gate of a MOSFET transistor. The MOSFET is like an amplifier in that it takes the small charge at the input and controls a larger signal without depleting the input charge. Think of the cell as a light switch: the switch stays in the same position no matter how much electricity passes through. The part that stores the charge and makes the flash MOSFET different from a normal MOSFET used in other electronics is called the floating gate. This is made of layers just a few atoms thick of insulators and conductors.

The catch is in programming and erasing the cell. To make the flash cells last, you need to eliminate any possible conductive path in or out of the charge storing part of the cell. Programming a flash cell to a 0 (flash is a “1” in it’s erased state, the N in NOR and NAND flash stands for “not”, i.e. negative logic) requires pushing a high voltage onto the MOSFET, causing it to conduct just enough to push some electrons into the MOSFET’s floating gate. Erasing requires an even higher voltage applied in a different way to drain the charge out. Both processes take advantage of normally undesirable features of MOSFETs called breakdown, where a high enough voltage causes it to conduct in ways it wouldn’t in normal operation.

Those high voltages, particularly the erase voltage, cause permanent wear on the floating gate and MOSFET, causing the charge to leak faster than normal. Even flash that’s not written or erased often isn’t perfect and a programmed cell will degrade over many years from a 0 to a 1. There is a whole science to counteracting flash wear and inevitable errors that I won’t go into here. The SSD controller chip is responsible for managing wear and data integrity, which is why you sometimes hear about SSDs that could lose your data if you don’t have a bugfixed firmware.

There are other technologies that are available that could replace flash. MRAM stores magnetically and is immune to wear from writing, not unlike core memory used in computers from the '50s through the '70s. FeRAM is similar to MRAM but less dense. You already have FeRAM in your car’s dash to store the constantly updating mileage, as it’s immune from damage by that constantly updating number or automotive temperature extremes. Phase change memory stores by heating tiny chunks of a crystalline material to get it to change it’s structure. Intel used this in its now-defunct 3D Xpoint memory. Memristor is another that takes advantage of a relatively new kind of electronic component type.

All of these new technologies are better than flash in longevity and many are close to RAM in performance. However none yet can be made as dense as RAM or as cheaply as flash. Memristor and MRAM are both frontrunners for replacing both RAM and flash, but it’s only fairly recently that fabs started offering the processing steps needed to make these in high density devices.